Power Optimization of KNN Algorithm Based on FPGA

In modern Field Programmable Gate Array (FPGA) digital systems, power dissipation has become a critical concern to design digital systems. As size shrinks and density increases in chips, it will be a challenge to design high-performance and low-power digital systems. Therefore, it is important to reduce the power dissipation in these systems by using power-optimization techniques. Most digital systems have different mathematical operations and machine learning algorithms in their architectures. This paper focuses on K-Nearest Neighbor (KNN) algorithm. A KNN algorithm takes more extended time, larger area and consumes more power than other basic computational algorithms. Thus, recent digital systems require high speed and low-power KNN algorithm in order to improve its performance. In this work, dynamic-power consumption is targeted. Different designs of KNN algorithms, such as KNN design Based on Hard FPGA Blocks, Hybrid KNN Design, and KNN Algorithm Based on the VHDL Approach are suggested. A new power-optimization technique is suggested. The new VHDL technique shows the highest dynamic power saving, about (90%) than the other proposed designs.