Design of FinFET and GnrFET Based Full Adder Cell Using Multiplexer Selection Logic

As transistor dimensions shrink to sub-micron sizes, new difficulties like as power efficiency and unnoticed radiation impacts have become major concerns in the field of very large-scale integration. Further, Complementary Metal oxide Semiconductors (CMOS) transistors are consuming the higher area, power, and delay consumptions. Thus, A novel 10 Transistor (10T) full adder is designed and simulated using both Fin field-effect transistors (FinFET) and graphene nano-ribbon field-effect transistors (GnrFET), which is one of the potential solutions to tackle issues generated in the conventional CMOS. Further, the proposed full adder is functioned based on the multiplexer selection logic, which can effectively reduce the path delays and number of transistors. In addition, 4-bit ripple carry adder (RCA) also developed using proposed full adders. Finally, the simulations are carried out using HSpice simulation tool with 7nm, 10nm, 14nm, 16nm and 20nm based FinFET libraries and 22nm based GnrFET libraries. The simulation results showed that the proposed method resulted in superior performance as compared to the state of art approaches.