High Performance VLSI Architecture of Multiplexer and Demultiplexer Using various Adiabatic Logic

Using adiabatic logics, we proposed the design and evaluation of a 1:16 Multiplexer and a 16:1 De-Multiplexer in this paper. We used traditional static CMOS logic to implement a 1:16 Multiplexer and a 16:1 De-multiplexer to compare the strength of static cmos logic and adiabatic logic. In many vlsi designs, power consumption is the most important factor. We used adiabatic logics to implement a 1:16 Multiplexer and 16:1 Demultiplexer in static CMOS logic to minimize power consumption. The adiabatic logics are 2N2P and 2N2N2P where in both the adiabatic logics use cross-coupled transistor for adiabatic operation. Adiabatic logic uses reverse logic and energy recovery technique that results in less power dissipation when compared to static CMOS logic. In static CMOS logic, we will give constant power source as Vdd. So, the total energy gets dissipated across the resistor, the energy stored by the capacitor will be very less because of this energy recovery is not happened as in case of static CMOS logic. In adiabatic logic we will give slowly varying ramp signal as vdd. So, the total energy is not dissipated across resistor and the capacitor starts charging. In the discharging phase the energy stored by the capacitor is sent back to the source because of this energy consumption is reduced. This is the energy recovery technique which happens in adiabatic logics.