Efficient Design of Multiplier using EGDI Technique

The current tendency is to look at the possibility of using high-speed, low-power arithmetic components for Video, Image, and Voice processing. Vedic Multiplier (VM) can increase the speed of operation three times compared to conventional Wallace Multiplier. The Architecture of Enhanced Gate diffusion Input (EGDI) is more amenable to Vedic Multiplier than the standard Architecture and a power-saving architecture based on Gate Diffusion Input (GDI). This paper has presented various VM-based arithmetic elements utilizing EGDI, GDI, and CMOS through 130 nm CMOS standard Library of Mentor Graphics. The results have been compared with conventional CMOS, GDI and fixed to be a very encouraging process VM-EGDI as a formidable contribution. Finally, design an FIR using VM-EGDI reduces the 18%-37%, 50%-75% of power and delay compared to FIR using VM-GDI and VM-CMOS.