CNN based Design Rule Checker for VLSI Layouts

Design Rule Checker (DRC) is one of the most important tools of modern VLSI layout design. DRC involves the checking of design rules in a VLSI layout. In recent developments of chips with an even lower channel length of the transistor, the number of DRC violations has increased from a few hundred to thousands, thus checking so many DRC violations has become a critical point in the layout generation of custom circuits. Many industries came up with different approaches to tackle this problem and to make the DRC forming and checking stage faster. Since the evolution of Machine Learning, researchers from every field of engineering & even from management are relying on various machine learning algorithms to make existing processes faster and more accurate. This paper is aimed in the same direction, which is to implement a machine-learning algorithm to make the DRC checking and execution process faster and more accurate concerning existing processes. This paper is aimed to propose a different approach to implement DRC which is based on Convolutional Neural Network (CNN) model technique. The layout violations in the circuit will be detected by our trained CNN Model, specially trained for some specific layout violations in a circuit. The proposed model is successful in the detection of the design rule constraints in a layout with an accuracy of 98% and can be expanded to larger and more complex layouts. The current scope of this paper includes hundreds of layouts for 3 different logic circuits and the accuracy obtained is quite encouraging.