Two Speed Modified Radix-4 Booth Multiplier With Different Adder Configurations

In this proposed system, a two speed modified radix-4 booth multiplier algorithm with different adder configurations are implemented for the applications like digital signal processing, digital filters and other neural networks. This multiplier is a modified version of a n-bit serial multiplier which performs booth multiplication algorithm which adds the nonzero computations and skips all other all-zero all-one computations. The datapath of the multiplier is partitioned into two subcircuits operating with two different critical paths which includes a control circuit for operating skipping and a combinational circuit for multiplication. Various adder configurations are utilized in this two speed multiplier and compared in terms of speed by propagation delay and area by number of slice LUTs. The proposed multiplier is designed using verilog HDL and evaluated on Xilinx ISE 14.7 Simulator.