Design of a low power and high-speed Viterbi decoder using T-algorithm with normalization

There is an ever increasing demand for low power and high speed error control decoders in digital communication systems. Viterbi decoder, used for decoding convolutional codes finds extensive use in wireless communication systems. This paper deals with the design of a low power and high speed pipelined Viterbi decoder using T-algorithm with normalization, aimed towards decoding high constraint length convolutional codes. When high constraint length convolutional codes are used, the error correcting capability of the decoder increases but at the cost of increased decoder complexity and reduced speed of operation. To reduce the complexity and hence reduce power and area, the number of bits used to store the path metric value of the decoder is decreased. To overcome the performance degradation due to the truncation of storage bits, a `high bit clear’ normalization circuit is used in the proposed work. From the results, it was observed that a rate 1/2 decoder with a truncated 6-bits wide path metric value along with the normalization unit occupies 20.90 percentage less area and consumes 18.18 percentage less power as compared to a decoder using nineteen path metric bits. Apart from low power operation, the design speed is also increased by designing the normalization unit in a pipelined fashion. For the same rate 1/2 decoder, the maximum speed of the decoder increases from 4 MHz to 5.6 MHz due to the implementation of the normalization block in a pipelined fashion. It is envisaged that this low power and high speed Viterbi decoder will play a significant role in applications including wireless sensor networks and mobile communications.