Low Power 90 nm 8 × 4 Pseudo NMOS Barrel Shifter Design

In this paper, the authors implemented an 8×4 barrel shifter using two MOS logics: static CMOS and pseudo NMOS. Cadence Virtuoso is used for simulation at 90nm technology. Parameters such as power consumption, delay, Power Delay Product were calculated using the cadence Virtuoso tool. The simulation results show that the power consumption of a barrel shifter designed from Pseudo NMOS is 33.5% more efficient than the barrel shifter designed from a static CMOS-based design.