Leakage Minimization in Semiconductor Circuits for VLSI Application

Battery operated devices spend the majority of the time in standby mode (sleep mode). Achieving the proper power dissipation especially leakage power has become a challenging factor in low power VLSI design as with scaling the transistor size doubles every two years satisfying Moore’s law. The sub-threshold leakage current of transistor has increased dramatically as the threshold voltage Vth has been reduced, resulting in leakage (static) power dominating dynamic power. This paper deals with various techniques for decreasing the leakage power in deep submicron CMOS circuits. Various leakage reduction techniques such as Sleepy stack, Forced stack, Lector, Galeor, Input vector control, Sleepy Keeper are implemented for combinational circuits such as an INVERTER, NAND gate and NOR gate. The logic gates are designed using 90nm technology and simulated using Cadence Virtuoso tool. Comparative study of dynamic power, static power and delay is accomplished.