Implementation and comparison of Boolean logic for different Nano Scaling technologies

We have designed logic of (A+B)C’ in this paper using CMOS, DOMINO and Pass transistor logic gates at different Nano scaling technologies. For any low power VLSI design, when compared to test mode, the circuit’s power dissipation is lower in regular mode of operation. This intern decreases the device’s battery life. As a result, in today’s VLSI circuit design, during regular operation, reducing power dissipation has become a priority. In terms of power consumption, the performance of DOMINO, CMOS and pass transistor gates is investigated. In comparison to traditional approaches, CMOS, DOMINO and Pass Transistor gates utilize less power, according to simulation data.