Power Dissipation of Adiabatic Logic Circuit for FinFET and MOSFET Transistors

Technology has turned things around in the microelectronics world and Integrated Circuit (IC) has been the driving force behind all these innovations. A lot of improvements have been made since the inception of the IC with the goal of improving performance of an IC. However, as the number of transistors on a chip increase with the goal of improving performance, it comes with a major drawback of more power dissipation. To address these challenges, this study investigates the energy efficiencies between two different types of adiabatic logic families, implemented with Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Fin Field Effect Transistor (FinFET) 32 nm technology node. LTSPICE (SPICE based analog electronic circuit simulator computer software) is used as the simulation tool to evaluate the power dissipation between both the Energy Charge Recovery Logic (ECRL) and the Positive Feedback Adiabatic Logic (PFAL). The results obtained revealed clearly that the Energy Charge Recovery Logic (ECRL) Inverter and NAND gates dissipate more power than the PFAL Inverter and NAND gate using MOSFET transistor. On the other hand, the power dissipated for the ECRL NOR gate is less than the PFAL NOR gate. Furthermore, the experimental results demonstrate that for all gates configurations (Inverter, NOR and NAND), ECRL dissipate less power than the PFAL using the FinFET transistor.