Formulae and applications of interconnect estimation considering shield insertion and net ordering

It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an area-efficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in the min-area SINO/R solution. In order to accommodate pre-routed P/G wires that also serve as shields, we then formulate two new SINO problems: SINO/SPR and SINO/UPG, and propose effective and efficient two-phase algorithms to solve them. Compared to the existing dense wiring fabric scheme, the resulting SINO/SPR and SINO/UPG schemes maintain the regularity of the P/G structure, have negligible penalty on noise and delay variation, and reduce the total routing area by up to 42% and 36%, respectively. Further, we develop various pre-layout estimation formulae for shielding areas and optimal P/G structures under different routing styles. These formulae can be readily used to guide global routing and high-level design decisions.