An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires

This article presents a receiver (RX) with an input-level-sensing clock and data recovery (CDR) circuit for a C-PHY interface with trio wires. The proposed CDR circuit detects a “strong” signal from the clock-embedded three-phase-coded signals and recovers the 3-bit wire state and clock simultaneously based on the detected “strong” signal without the inherent switching jitter of conventional C-PHY RXs. Also, the proposed input-level-sensing circuit allows for low power consumption and small size by detecting a “strong” signal without reference voltage or static current consumption, and it automatically compensates for the gain of the analog front end to remain just high enough to detect a “strong” signal even with process, voltage, and temperature variation. This work is implemented using a 28-nm CMOS process with a 1-V supply and occupies an area of 0.022 mm², achieving a total energy efficiency of 0.93 pJ/bit at 18.24 Gb/s.