Analysis of the subthreshold shift induced by the shallow trench isolation corner in advanced DRAM and flash memories

We have analyzed the effect of shallow trench isolation on transistor performance in state-of-the-art memory circuits. Gate wraparound, corner rounding, and gate oxide thinning are all significant factors that affect the electrical performance. We have identified gate wraparound as the main contributor to the subthreshold shift of the NMOS transistors.