VLSI Design of Low Power $8\times 4$ Barrel Shifter using 90 nm TG technology

The barrel shifter is known for the manipulation of various bits in a single clock cycle. In this paper, an
$8\times 4$
barrel shifter is designed using transmission gate technology. The design and simulations are carried out using the cadence virtuoso tool at 90 nm technology. The simulation results show that the power consumed by the proposed design is 51.5% more efficient than the barrel shifter designed from CMOS NAND-based multiplexer design. Hence this design can be used in the application of low-power digital communication.