An Efficient Application Core Mapping Algorithm for Wireless Network-an-Chip

With the large number of processors in the chip, the design of a well-organized communication framework is crucial to satisfy the energy and bandwidth of multi-core systems. Network-on-Chip (NoC) has become the standard communication outline to replace the bus networks. Wireless NoC is becoming well known to be an auspicious upcoming on-chip communication framework because of low latency and high bandwidth provided by this emerging technology. Mapping vertices on various cores of the network is a critical segment in Wireless NoC because it decides the communication energy and latency. To diminish the communication energy of application core graph on multi-processors architecture, we propose an efficient application core mapping algorithm for Wireless NoC, that maps the application cores on Wireless NoC platform based on preliminaries. Which has three key steps: finding the efficient mapping region, selecting the first vertex to be mapped and choosing the suitable core on the Wireless NoC platform. Our empirical evaluation shows that, the proposed efficient algorithm averagely reduces packet latency 12%, 18% and 25%, and communication energy 17%,23%,28% over the RRM [14], DAMA [13] and MCDM [11].