A Reversible-Logic based Architecture for VGGNet

Computer vision is witnessing increased usage of Convolutional-Neural-Network (CNN) deep learning architectures. Researchers have experimented with more complex architecture variants of CNN, such as VGGX, GoogleNet, and ImageNet to correlate depth of architectures, especially convolutional blocks with model accuracy. Such architectures are extensively used in complex object classification and computer vision problems such as self-driving cars, surveillance, and security systems. However, the drawbacks are high computational cost, area overhead, and excessive power dissipation since the operations involved under CNN architectures are both computationally and memory extensive. This work proposes a novel design fully reversible-logic based VGGNet architecture for low-power VLSI (Very-Large-Scale-Integration) circuit synthesis. We have implemented two architecture variants of VGGNet, as RL-VGG-16 and RL-VGG-19 using only reversible logic gates and circuits. Ideally, no information can be erased during reversible logic operations. Therefore, reversible circuits generally do not dissipate any heat. The proposed architectures have been implemented using VHDL on Altera Arria10 GX FPGA. The comparative analysis demonstrates that proposed RL-VGG-16 architecture achieves approximately an 18.08% decrease in overall power dissipation compared to the classical VGG-16 architecture. The proposed RL-VGG-19 architecture achieves approximately a 16.48% decrease in overall power dissipation compared to classical VGG-19 architecture. Both proposed approaches also have better scalability than the classical design approaches.