CORDIC Accelerator for RISC-V

Software Defined Radio (SDR) is a highly configurable transceiver that provides flexibility in communication systems. The flexibility of SDR is achieved by implementing most of the SDR architecture in software. The software of the SDR is responsible for the modulation/demodulation of messages and frequency conversion of the signals. These operations frequently use Sine and Cosine functions. Sine and Cosine functions are required to be stored in memory or to be calculated. Storing these values in the memory causes a decrease in core performance. Sine and Cosine functions can be calculated with Coordinate Rotation Digital Computer (CORDIC) algorithm or Taylor’s Series. Taylor’s series consists of multiplication and division operations which are hard to implement in hardware. This study proposes an accelerator that calculates Sine and Cosine functions with CORDIC algorithm. The architecture of the accelerator is based on systolic array architecture to allow the core to acquire the functions’ value immediately. The result shows that the proposed system provides at least 32x speed up over Taylor’s Series having grade 4. While providing speedup, the proposed accelerator increases the resource usage of the bare system as around 5,5% and power consumption of bare system as around 8%.