Hardware Accelerators for Calculating the Magnitude and Angle of Image Gradient

This paper presents the problem of using digital image processing algorithms on embedded processors. The issue is common when processing a large stream of data in edge detection of images and videos. Calculating the magnitude and angle of an image gradient is essential for edge detection, which is why these paper deals with the practical problems in implementing this algorithm. The system is implemented in two phases, first only in software with an embedded processor and second with the realization of specific hardware accelerators in FPGA that aid the software where bottlenecks significantly slow up the system. The implementations of all algorithms are in fixed-point representation, as well as the image that is being processed. Special algorithms that are used in this project include CORDIC and square root fixed point calculation. The system results are discussed and further improvements are proposed.