A Compact Modeling Methodology for Experimental Memristive Devices

A methodology to create and develop electrical compact models for memristive devices is presented. It comprises a six-step algorithm that uses experimental data of memristive devices in order to obtain a compact model suitable for circuit-level simulations. The model methodology makes use of the definition of the intrinsic variables of memristive systems, to obtain the state map that describes the system, from which the mathematical expressions of the model are obtained. In order to illustrate the usage of the algorithm, a compact memristive model is developed by using experimental data from a TiO2-based resistive switching (RS) device. The resulting mathematical model is compared to the experimental data by computing the mean absolute percentage error (MAPE) between both, which results in 11%, and reduces to 6% after a piecewise approach. The circuit-level representation is implemented using a SPICE macromodel and a Verilog-A module, from which the memristive behavior is also properly reproduced.