Positive Bias Temperature Instability and Hot Carrier Degradation of Back-End-of-Line, nm-Thick, In2O3 Thin-Film Transistors

Recently, back-end-of-line (BEOL) compatible indium oxide (In
₂
O
₃
) thin-film transistors (TFTs), grown by atomic layer deposition (ALD) with channel thickness of ~1 nm and channel length down to 40 nm, have achieved a record high drain current of 2.2 A/mm at
${V}_{\textit {DS}}$
of 0.7 V. A systematic characterization of the reliability issues, such as positive bias temperature stress (PBTS) and hot carrier degradation (HCD), would allow its immediate integration into innovative ICs, such as 3D-stacked SRAM or on-chip bridge for mixed-voltage systems. Surprisingly, PBTS and HCD are both characterized by a universal two-stage threshold voltage shift (
$\Delta \!{V}_{\textit {th}}$
, a positive shift followed by a temperature-activated negative shift). This is attributed respectively to electron trapping/trap-generation and hydrogen-assisted formation of donor-traps. These competing mechanisms of
$\Delta ~{V}_{\textit {th}}$
depend on the stress voltages and stress temperature. Unlike traditional logic transistors, HCD in BEOL-TFTs is strongly correlated to PBTS, caused by the much stronger vertical field in an ultra-thin device. Overall, this high-performance BEOL-transistor is remarkably reliable, with a relatively small
$\Delta ~{V}_{\textit {th}}$
under PBTS/HCD stress conditions at room temperature (RT). However, self- and mutual heating of BEOL interconnect levels and the resultant threshold voltage variability must be mitigated/managed for its successful integration in various neuromorphic circuits.