ESD Circuit Simulation by SPICE

The foundation for SPICE‐type circuit simulation is device modeling for which Berkeley short‐channel IGFET model device modeling technique is probably the most successful and widely used device modeling technique in analog and mixed‐signal IC designs. The grand technical barrier to realizing full‐chip electrostatic discharge (ESD) protection circuit simulation using transistor‐level circuit simulation tool, such as SPICE, is the lack of general and accurate ESD device models. ESD device behavior modeling accurately describes the measured ESD discharging I–V characteristics for any ESD protection structures fabricated. Circuit‐level ESD protection simulation using SPICE will be able to optimize and predict full‐chip ESD protection circuit designs by ordinary IC design engineers without much pain as typically associated with conducting technology CAD ESD design simulation. SPICE‐based full‐chip ESD zapping test simulation offers ordinary IC designers a powerful means to check if the ESD protection design will work for a specific IC chip.