Simulations and Measurements of Failure Modes in SiC Cascode JFETs under Short Circuit Conditions

Using experimental measurements and finite element simulations, this paper investigates the failure mode of SiC Cascode JFETs under short circuit (SC) conditions. Unlike SiC MOSFETs, where failure results in a shorted gate-source terminal (resulting from gate oxide failure), in SiC Cascode JFETs, failure usually occurs in drain-source short with the gate of the Low Voltage (LV) silicon MOSFET still operational. Measurements show that after the LV Si MOSFET gate is turned OFF, a high tail current results in the Cascode drain terminal with the drain-source voltage falling to approximately half of the blocking voltage, suggesting that the JFET is in linear mode. Finite element simulations show that thermally generated carriers in the JFET depletion region cause high leakage currents through the internal JFET gate terminal capable of turning-ON the JFET (after turn-OFF of the LV Si MOSFET) into linear mode. The measured short circuit withstand time (SCWT) is shown to be independent of temperature unlike silicon MOSFETs where the SC withstand time increases with the initial temperature.