Dynamic and Capacitive Characterization of 3D GaN n-p-n Vertical Fin-FETs

Gallium Nitride (GaN) vertical n-p-n 3D nanostructured transistors have been demonstrated to be excellent normally OFF devices, making them exploitable for next generation power converters. However, their stability is still under investigation.The aim of this work is to present one of the first studies on the performance and stability of n-p-n vertical FinFETs, to contribute to the understanding of the related physics. Devices show positive threshold voltage of 3 V, that was found to be affected by positive bias temperature instability. The analysis conducted reveals the presence of a trapping process with activation energy of 0.30 eV, which is ascribed to defects at the semiconductor-oxide interface. Capacitance-voltage measurements and TCAD simulations were used to gather further information on trapping phenomena and device’s working behavior.