High-throughput high-density mapping and spectrum analysis of transistor gate length variations in SRAM circuits

High-throughput high-density mapping of gate length variations using static random-access memory (SRAM) as electronic test structures is reported. In the experiments, direct measurements of bit-line currents revealed the individual transistor gate length variations within every memory cell. With SRAM and its fast addressing circuits we can measure CD variations with measurement time as fast as 5 /spl mu/s per data point and spatial periodicities down to 6 /spl mu/m. Layout-dependent periodic errors were found to take up 30% to 90% of the total observed error variance, depending on the spatial frequency range and specific measurement grid used. Peaks in the error spectrum were found to be related to the periodicities existing in the circuit layout. Lithography simulations were done as efforts to identify the periodic error sources. It was found that proximity effects and pattern-dependent coma effects contributed to a large percentage of the high spatial frequency errors observed. By independent optical measurements of the poly mask, it was found that the CD error contributions from the mask are very small, and are negligible when compared to the stepper-lens-induced CD errors.