Design and Implementation of Power and Area Efficient Phase Frequency Detector

Recent development in VLSI and CMOS technology has led to numerous power reduction techniques. This edge has helped in the implementation of the Phase Locked Loop (PLL) for wireless communication applications. The first block of a PLL structure is the Phase Detector which acts as a bottleneck to the entire system thereby affecting the speed and performance of the PLL. Phase Frequency Detector (PFD) operates at very high frequencies and consumes more power. Two low power PFD architectures are proposed in this work. The proposed-1 PFD uses Inverter and two input NAND gate with LECTOR technique to reduce leakage current. The proposed-2 PFD uses a Double edge triggered D-flip-flop with pulse-clocked and TSPC logic which consumes the least power among all the implemented architectures and also requires less transistors. The PFDs circuits are implemented in CMOS 180nm technology using Cadence Virtuoso and simulated in Cadence Spectre with 1.8V supply voltage and operating frequency at 20 MHz. Performance of reference and proposed PFD circuits are analyzed w.r.t. to power and area (transistor count). The results inferred reduction in the power consumption when compared to reference architectures and operate at higher frequency.