Design and Implementation of FPGA Based Dynamically Re-Configurable Processor for Machine Learning Systems

The System On Chip has problems related to growing the scale of circuits and reducing the design costs, due to many kinds of application-specific hardware modules. In this paper, dynamically reconfigurable multiprocessor architecture suitablefor decision trees (DTs), artificial neural networks (ANN s), and support vector machines (SVMs), for field-programmable gate arrays (FPGA), has been realized. The proposed objective is to overcome by using a way of reconfigurable gadgets such as Field Programmable Gate Arrays (FPGA). Dynamically reconfigurable processor structure with an RFU format applied to Xilinx ISE is proposed. It consists of a processor, memories, buses, controllers, and dynamically reconfigurable RFU. We employed a multi-bus machine and designed the controllers for a dynamical reconfiguration. Implementation and Evaluation are performed on Virtex-6 FPGA for circuit measurement and reconfiguration time. The effects showed that the partial reconfiguration time was once small enough. The proposed work is simulated in Xilinx ISE 14.7 and achieved less delay 8.142ns.