Hard-Switching Losses in Power FETs: The Role of Output Capacitance

For certain field-effect transistors (FETs) in soft-switching operation, the large-signal behavior of their output capacitance (
${C}_\text{o}$
) has shown to deviate considerably from the datasheet values. This can have a significant effect on hard-switching losses if the value of output charge is also different for a given voltage. In addition, standard hard-switching tests are incapable of fully setting apart the contributions from
${C}_\text{o}$
, whereas existing methods tailored to characterize
${C}_\text{o}$
losses in soft-switching operations subject
${C}_\text{o}$
to a fundamentally different charge–discharge process, and hence, might not predict the correct behavior for hard switching. To address this, first, we analyze and establish the particular charge–discharge conditions that
${C}_\text{o}$
undergoes in hard-switching circuits by considering a half bridge at no-load conditions. We show that the channel of the switching device incurs a fixed energy loss during the turn-
on
process, which is separated into co-energy and stored energy components of the top (complementary) and bottom (switching) devices, respectively. Exploiting this, a new measurement technique is developed to obtain output-charge versus voltage curves of devices subjected to actual hard switching. The experimental results for commercial Si, SiC, and GaN devices indicate that the effective charge-capacity of
${C}_\text{o}$
for hard switching can considerably vary from the values based on datasheets or Sawyer–Tower circuit; this could greatly undermine efficiency and thermal optimizations in the design phase of power converters.