Measurement and simulation of the three-dimensional temperature field in an RF SOI chip

We present in this study a novel way to determine the three-dimensional (3D) temperature field o f a R adio Frequency Silicon On Insulator (RF SOI) electronic chip, using several resistance temperature detectors (RTDs) embedded at different locations of the chip. The RTDs are designed and placed at different locations to experimentally obtain the temperature at key locations of the chip enabling the calibration of a multiphysical numerical model that provides the 3D temperature field in the whole chip under operating conditions. The obtained results provide useful insights on the role of different parameters (e.g. used materials properties, heat source power, substrate, boundary conditions, etc.) to engineers interested in the modelling and optimization of heat transport and thermal management of electronic chips for RF applications.