Return Loss Optimization of 25-Gbps High-Speed Serial Link on a Multilayer PCB

Optimizing return loss for vias and high-density BGA (Ball Grid Array) areas is becoming important as signaling speed increases. Designing high speed PCB (Printed Circuit Board) without field solver simulations can cause severe SI (signal integrity) problems. In this paper, design and simulation methodologies are adopted to optimize 25 Gbps (Gigabit per second) high-speed serial links on a multilayer PCB. To improve signal integrity, return loss is lowered using two primary strategies. Initially, a differential via anti-pad impedance is optimized in a high-speed connector through a 3-D field solver approach. Then, advanced PCB layout techniques for BGA signals breakout (fan out) are employed from the ball to the outside of BGA area, and effectively demonstrated using field solver results. Therefore, an overall return loss improvement of approximately 8 dB is achieved between 5 to 7 GHz, enabling the design to pass 25GBASE-KR normative mask with a good margin.