An Optimized FPGA Based Box-Muller Gaussian Random Number Generator Architecture for Communication Applications

This paper presents an efficient Box-Muller GRNG (Gaussian Random Number Generator) structure to reduce the FPGA (Field Programmable Gate Array) logic utilization. The proposed approach is mainly targeting communication applications. We focus on optimizing the throughput. The FPGA Block RAMs (BRAMs) are associated to multiplexer for reducing the required memory size and producing the Box-Muller logarithmic function. The uniform random variables and the multiplexer selector are produced by an LFSR (Linear Feedback Shift Register) based unit. According to this approach, we can reduce the required memory size along with keeping the conventional accuracy. A Xilinx FPGA device is used for validation. The obtained results show that the proposed Box-Muller GRNG structure offers reductions of memory size from 4M to 6K and from 8G to 10K for tail of 5.52σ and 7.81σ, respectively when implemented on a Xilinx FPGA device. Furthermore, a similar high accuracy for the conventional Box-Muller GRNG is achieved with a reduced FPGA slice utilization.