High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor With Top Gate to Drain Offset

We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset (
$\text{L}_{\text {TG(Off)}}$
) structure under dual-gate driving. The TFT shows an on/off current ratio of
$\sim 10^{{7}}$
, subthreshold swing of 0.23 V/dec, and field-effect mobility (
$\mu _{\text {FE}}$
) of 14.6 cm
²
/Vs when
$\text{L}_{\text {TG{(}Off{)}}}$
is 5
$\mu \text{m}$
, which is 30% reduction compared to the conventional DG TFT with no drain offset (
$\mu _{\text {FE}}=20.9$
cm
²
/Vs). The Technology computer-aided design simulation indicates the electron concentration of
$\sim 10^{{16}}$
/cm
³
at the offset region near top gate insulator/a-IGZO interface when
$\text{L}_{\text {TG{(}Off{)}}}$
is 5
$\mu \text{m}$
. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.