SoC Verification For The AXI Interconnect Based on The Static Fixed-Priority Scheduling Algorithm

Any SoC digital design can be simulated, synthesized, and implemented using HDL languages. The SoC verification on the target device for any SoC digital design is a very important step before the design tap-out. In such cases, the SoC digital design specifications are larger than the target device resources. Increasing the Input/ Outputs of the digital design is such of these SoC difficulties when they are more than the Inputs/ Outputs of the SoC target device. In the previous work, an AXI interconnect was designed based on the static fixed-priority scheduling algorithm to connect four masters and one slave using the AXI4 interface protocol. To verify the AXI interconnect on the FPGA ZedBoard, a problem occurred: the Inputs/ Outputs of the AXI interconnect were more than the Inputs/ Outputs of SoC target device. In this paper, we have converted the HDL design code to the IP core to solve the increasing number of Inputs/ Outputs. This solution has kept the SoC verification of the AXI interconnect on the FPGA ZedBoard easily. The verification of the design is successfully done on FPGA ZedBoard (xc7z020clg484-l) using the Vivado tool.