Designing Of Low Power Clocking Scheme Based Energy Revival Sense Amplifier Flip-Flop

There are lots of challenges to surmount to be capable to keep on the increasing the amalgamation at the same place in a single IC chip. Key challenges are rising power dissipation due to clock networks, rising seepage currents that results in static power dissipation and abridged circuit heftiness. In the SOC systems, the major dominating contributor for the total power dissipation is the power that has been dissipated during clock generation. The rising complexity of SOC systems is directly proportional to rising clock power. This enables novel power reduction techniques completely important in further VLSI designs. This work presents an innovative clock generation technique that aims to help in reduction of delay and also power dissipation. Proposed clock generator has reduced the delay to 30% in sense amplifier based ER flip-flop.