Efficient Multiplier Architecture for ECC Core

High significance of elliptic Curve Cryptography (ECC) has been seen in many applications over the years since its development in 1986. ECC is widely utilized for security academies, design protocols, device security, arithmetic algorithms and structures etc. Due to its shorter key length, ECC has becomes first choice for many IoT and electronic devices. However, enormous enhancement of cyber-attacks and crimes in digital market has provided a necessary reason to make ECC more robust and stable to handle this kind of threats i.e. a major enhancement in ECC core is a necessity. Therefore, this paper introduces a High Throughput Concurrent Computation (HTCC) technique for Elliptic Curve point multiplier architecture. The synthesis using the proposed HTCC technique is performed on Xilinx Virtex – 5 and Xilinx Virtex – 7 FPGA over GF(2
¹⁶³
). The efficiency is increased by 75.31% for Xilinx Virtex – 5 and 47.75% using proposed model for Xilinx Virtex – 7. The resource utilization is decreased by 65.80% for Xilinx Virtex – 5 and 67.59% using proposed model for Xilinx Virtex – 7. The performance results are satisfactory for the factors like timing, resource utilization, frequency and latency of the architecture.