Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate–Source Underlap

Bipolar Impact Ionization MOSFETs (BI-MOS) are promising devices because of abrupt OFF-ON transition and lower breakdown voltage compared to a conventional I-MOS. Nevertheless, the breakdown voltage of a BI-MOS is $\sim 2.8 V$ and needs to be further reduced. In this paper, using a calibrated simulation model, we demonstrate that by employing an optimum gate–source underlap, 25% reduction in the breakdown voltage can be obtained. The gate–source underlap creates a spike in the electric field in regions where impact ionization is initiated. Thus, it aids the breakdown phenomenon and reduces the breakdown voltage. Furthermore, we employ the proposed technique on a double gate bipolar junctionless impact ionization MOSFET (DG BJI-MOS). We demonstrate that a 17% reduction in the breakdown voltage can be obtained by gate–source underlap and the breakdown voltage in the proposed device reduces to $\sim 1.5 V$.