CMOS ISFETs With 3D-Truncated Sensing Structure Resistant to Scaling Attenuation and Trapped Charge-Induced Offset

With helps of advancing CMOS technology, ISFETs have achieved great success. However, CMOS-based ISFETs are also suffering problems of scaling attenuation and threshold voltage offset. These problems mainly result from the architecture used to adapt standard CMOS process. To deal with these, we developed a novel CMOS ISFET configuration, namely, 3D-T-ISFET, by building a truncated architecture to expose CMOS process-inherent TiN thin film as the sensing interface. Due to the electrical conductivity of TiN, the signal from the environment can bypass the sensing dielectric and couple to the transistor effectively through the electrical double layer capacitance. Based on our experiments, as the footprint of
$8.5^{2} {\mu } \text{m}$
²
, a 3.21-fold
${\Delta } \text{I}_{D}$
/pH improvement can be achieved by developed 3D-T-ISFET. At the same time, the 3D-T-ISFET has an about 1.65-fold improvement in SNR compared to the traditional 2D-ISFET. Compared to the 2D-ISFET in a state-of-the-art design, therefore, 3D-T-ISFET exhibits a scaling attenuation-free behavior and becomes less vulnerable to the non-idea effects brought by trapped charges.