Impact of High-k Dielectric Material on Ultra-Short-DG-FinFET Performance

The miniaturization of the SOI-MOSFET transistor reducesthe gate electrostatic control and reliability of the integrated circuit (IC). The fabrication of the transistor was reaching 7nm, but the scaling to 5nm technology node was projected to occur in the coming future, as a result, the researchers expect to identify new solutions for different design issues. In this paper, the double-gate FinFET for 5 nm technology is investigated with different gate dielectric materials (SiO2, SnO2, ZrO2, Ta2O5, and TiO2) using 3D-TCAD-SILVACO tools. The results showed that using TiO2 (k=85) as gate dielectric material produces better performance and excellent analog characteristics such as Vth, SS, Ioff, Ion/Ioff ratio, and DIBL. It discovered that the proposed device is the most compatible for improving device efficiency (reliability, lower power, manufacturing cost, and faster circuit) for the future of nanoscale devices due to the use of the high-k gate material TiO2, as well as a shorter gate (Lg=5nm). Furthermore, the maximum oscillator frequency (fmax) and cut-off frequency (ft) are both increased which makes the proposed device a delicate choice for RF applications and potential manufacturing process innovation.