An advanced CMOS process for university microelectronics laboratory courses

The manufacture of CMOS integrated circuits in a university laboratory course is difficult because the process is complicated and time consuming. At RIT, we have developed an approach that allows the manufacture of CMOS integrated circuits similar to manufacturing in a semiconductor factory. In this manufacturing approach, the students see all the steps in the process, including device electrical test. At the start of any lab course, there are many lots (each lot is 3 wafers) at different stages in the process. During the laboratory course, new lots are started as other lots are finished, keeping the total work in process (WIP) constant. Over the last year, we have introduced a new submicron CMOS process, which features dual well, n/sup +/ poly gate, sidewall spacers and low doped drain. Lambda based design rules for Lambda equal to 0.5 /spl mu/m give a minimum transistor length of 1.0 /spl mu/m with L/sub eff/ slightly less. One product is an analog/digital test chip. Factory performance was measured by computing Cpk's for approximately 30 process parameters, measuring cycle time, and evaluating electrical test results on completed lots.