A Memory-Based Direct-Digital Frequency Synthesizer for Fractional Synchronization

This brief presents a fully integrated energy-efficient memory-based direct digital frequency synthesizer (DDFS). To overcome the limitation of using an accumulator and a Read-Only Memory (ROM) Lookup Table (LUT) within a DDFS, the proposed design utilizes a 6-bit memory with a configured mode of operation to synchronize the digital output clock with the input sampling clock. The proposed DDFS is able to tune the output phase and frequency once a phase rotator is used in the input clock path. To realize the proposed DDFS, a 6-bit memory in front-end and some analog blocks in back-end are employed. The prototype DDFS achieves jitter below 12.7ps
$_{rms}$
integrated over a 100MHz bandwidth with 28.25Hz resolution while consuming less than 3mW at sampling clock 3.12GHz. The proposed DDFS is fabricated in a 0.9V TSMC 7nm CMOS process and occupies a core area of only 0.014mm
²
.