3-D Integrated Chiplet Encapsulation (3-D ICE): High-Density Heterogeneous Integration Using SiO2-Reconstituted Tiers

We propose a 3-D heterogeneous integration technology called three-dimensional integrated chiplet encapsulation (3-D ICE). The proposed 3-D ICE architecture encapsulates chiplets into a reconstituted tier using low-temperature (100 °C) inductively coupled plasma-enhanced chemical vapor deposition (ICP-PECVD) SiO
₂
deposition. The SiO
₂
-reconstituted tier in this work is 10-
$\mu \text{m}$
thick with through-oxide vias (TOVs) that are
$2 ~\mu \text{m}$
in diameter and
$10 ~\mu \text{m}$
in pitch (10
⁴
/mm
²
via density), which exceeds vias in conventional fan-out packaging. Tier transferring using KOH wet etch is also reported. Finally, the four-point Kelvin resistance measurements are performed for Cu-filled TOVs of various dimensions. The resistance of a 50-
$\mu \text{m}$
-diameter single via is 36
$\text{m}\Omega $
and that of a 2-
$\mu \text{m}$
-diameter via is
$1.14 \Omega $
.