Effect of Wafer Tilt During Ion Implantation on the Performance of a Silicon Traveling-Wave Mach-Zehnder Modulator

This paper reports a study of the effect of wafer tilt during dopant implantation on the performance of silicon PN phase shifter and traveling-wave Mach-Zehnder modulator. The PN phase shifter is designed and process simulated to include the effects of different fabrication processes in the device performance. The wafer tilt during implantation is varied from 0° to 3°, 5°, and 7°. The resulting crystal damage during dopant implantation to form the PN junction and the active concentration profile upon annealing, along with the formation of dopant–defect clusters, are discussed. Compared to 0° tilt, 7° tilt results in
$1.58\times $
higher phase shift and better modulation efficiency. The overall phase shifter performance is improved using 5° wafer tilt for implantation resulting in
$1.23\times $
lower absorption,
$1.45\times $
better modulation efficiency, and
$3.14\times $
higher 3 dB
$RC$
modulation bandwidth for lumped-driven phase shifter. A traveling-wave electrode to enhance the modulation bandwidth is used, and the modulator performance for non-return-to-zero on-off-keying modulation with–2.5 V bias and 2.5
$\text{V}_{pp}$
drive signal across each arm is evaluated using a dual-arm push-pull drive. The sample with 5° tilt shows better traveling-wave and modulator high-speed characteristics compared to the other samples. Among the four samples with different wafer tilts, the sample with 0° tilt shows the worst phase shifter performance, and the sample with 3° tilt shows the worst modulator characteristics. The best overall performance is obtained for the sample with 5° tilt. Compared to the modulator with implantation at 0° tilt, the 5° tilted sample shows
$2.3\times $
higher 6.4 dB electrical bandwidth and
$1.36\times $
higher 3 dB electro-optic bandwidth at–2.5 V using a traveling-wave electrode with
$1.48\times $
lower energy-per-bit for 5 km transmission at the KP4-forward-error-correction bit-error-rate threshold. The comparison of the effect of wafer tilt angles on various device metrics is presented and discussed.