Design of Low Power VLSI Architecture for Classification of Arrhythmic Beats Using DNN for Wearable Device Applications

Arrhythmia is one of the most common cardiac disorders, which is a critical threat to human life. However, wearable devices having real-time cardiac health monitoring aids individuals as well as medical professionals in the timely diagnosis of fatal heart diseases, such as arrhythmia. This paper proposes a low power VLSI architecture that facilitates the classification of Electrocardiogram (ECG) into normal and other seven types of arrhythmia beats using a Deep Neural Network (DNN). Unlike the existing methods for heartbeat classification, in which handcrafted ECG features are utilised, the proposed design leverages DNN for the classification of arrhythmia using a complete ECG beat. This obviates the need to extract ECG features separately and, produces an accurate and power optimised design for arrhythmia classification. Evaluation of the proposed methodology on the MIT-BIH dataset exhibits the accuracy and specificity of 97.01 % and 99.09%, respectively, which is comparable or better with respect to other algorithms implemented on software or ASIC based platforms. The proposed architecture is realised at 180nm CMOS technology having 0.624mm
²
area and exhibits 6.82× less power consumption at 1kHz as compared to others methods. The high classification accuracy and low power consumption of the proposed design make it suitable to be utilized in wearable devices.