Parasitics Analysis in the Power and Gate Driver Loops and Impact on the Ringing of SiC MOSFETs

This paper analyzes the behavior of transient switching silicon carbide devices influenced by the parasitics of printed circuit board and the component itself. The parasitics in power and gate driver loops are described and investigated. Double pulse test simulations for silicon carbide devices are conducted in this report and verified through the circuit simulation. The parasitics in the printed circuit board are added based on the real experience printed circuit board design and the parasitics in silicon carbide devices are added based on the manufacturer modelling. The parasitic inductances in the simulation are varied +/- 30% to understand the effect of the parasitics. The drain and source parasitic inductances and the gate parasitic resistance are simulated separately to understand the individual effect on the ringing of silicon carbide devices. The ringing impact on the reliability of devices is also analyzed in this paper.