A modified high speed and less area BCD adder architecture using Mirror adder

In number system, BCD numbers are well-known for representing numbers in four bit decimal format. Many circuits are designed and developed till today to work with the BCD numbers. In any processor or digital system adder plays major role in effecting the speed of operation of the whole structure. By executing BCD addition by means of BCD adder, the operation gets slow due to the delay in propagating the carry output from one stage to another stage of the adder. Also due to the usage of two RCA adders the area of the adder is also increasing. This delay is going to effect the operation and increasing the area of the entire system in which the BCD adder is used. To overcome this problem of delay and increase in area, a new technique of adder is proposed in this paper i.e., mirror adder. Mirror adder is an adder circuit which is implemented without using XOR gates. In this paper, BCD adder architecture is modified by replacing the 4-bit RCA with 4-bit mirror adder. The proposed design of adder is simulated and synthesized for various input bit sizes and then evaluated in terms of delay (ns) with the existing adders and area occupied (LUTs).