Design and Optimization of 4-bit Absolute-value Comparator Using CMOS & PTL Technique

In recent years, a rapid technological progress has been going on in the electronic industry, the level of integration and chip manufacturing process made significant progress within a few years' time. This causes a growing demand for swift and reliable devices design with low energy consumption. To achieve this goal, parameters like power dissipation and delay which are important roles of modern electronic device manufacturers have to be considered. In the paper, a hybrid design of a 4-bit absolute-value detector with the ability to compare the value of two inputs represented in 2‘s complement format is being done using Static CMOS logic, Pass Transistor Logic (PTL) and Transmission Gate Logic (TGL). The design uses the hybrid design described above to simplify the circuit and find a specific logic, especially for the absolute-value detect function, to reduce transistors. In order to prevent unexpected delays caused by the huge capacitive load driven at the output end, the design adopts an inverter chain as a buffer to avoid this situation. Based on the logic effort theory, this work transforms the capacitance and resistance of each gate into a ratio to a unit size inverter to find the total delay and energy consumption after locating the critical path. This study employs transistor sizing and power source (VDD) scaling technique to optimize the delay and energy consumption of the circuit towards different optimization goals (minimum delay or minimum energy with a delay less than 1.5 times of the minimum delay). These optimization strategies are simulated by MATLAB and LTSPICE software. The delay or energy consumption are represented by a ratio to that of a unit size inverter, then compared in the paper. A great improvement in the circuit performance has been shown in all optimization strategies, proving them to be practical and efficient designs for future use.