Design and Verification of Novel Sync Cell

A novel approach of clock domain crossing solution is presented. For high-frequency conditions traditional approach calls for multiple D-flops for single bit synchronization. The higher the frequency the higher the number of flops. In high-frequency solutions, such an approach can consume much-needed space and limit the useful area for additional logic. Hence a new mixed-signal circuit is introduced which can be used in high-frequency applications to reduce the overall area of synchronizer logic used for single-bit synchronization. Comparison has been done for traditional multi-flop synchronization and proposed design with analog comparators. Unlike traditional design, the proposed circuit has no additional delays in form of additional clock cycles. For the usual use case of a two-stage synchronizer, the proposed design has 20% more area, but in high-frequency applications, where three or more synchronization stages are used, at least 30% are reduction was achieved (the higher the stage number, the more reduction percentage). The simulation was performed with SAED 32/28 nm technology.