Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part II: Experimental

We present time-zero characterization and an investigation on bias temperature instability (BTI) degradation between 4 and 300 K on large area high-
${k}$
CMOS devices. Our measurements show that negative BTI (NBTI) on pMOSFETs freezes out when approaching cryogenic temperatures, whereas there is still significant positive BTI (PBTI) degradation in nMOSFETs even at 4 K. To explain this behavior, we use an efficient implementation of the quantum mechanical nonradiative multiphonon charge trapping model presented in Part I and extract two separate trap bands in the SiO
₂
and HfO
₂
layer. We show that NBTI is dominated by defects in the SiO
₂
layer, whereas PBTI arises mainly from defects in the HfO
₂
layer, which are weakly recoverable and do not freeze out at low temperatures due to dominant nuclear tunneling at the defect site.