Characterization of fully depleted SOI transistors after removal of the silicon substrate

FDSOI technology is compatible with the construction of three-dimensional integrated circuits. Removal of the silicon substrate, an essential step in the 3D assembly technology, will not cause an increase in off-state current provided the wafer bond technology is compatible with a 400/spl deg/C sinter. Substrate removal will also decrease the effect of ionizing radiation on transistor properties.