High-performance sigma-delta ADC for ADSL applications in 0.35 /spl mu/m CMOS digital technology

We present a sigma-delta modulator designed for ADSL applications in a 0.35 /spl mu/m CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use an oversampling ratio of only 16 . Special emphasis is placed on technology issues, e.g. poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2 MS/s and 12-bit dynamic range operating at 4 MS/s. The modulator consumes 77 mW from a 3.3 V supply and occupies 1.32 mm/sup 2/.